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 Professional ResumeQualifications Summary Over 20 years experience in all aspects of custom analog, digital and mixed-signal ASIC design including algorithm and architecture development, schematic entry/HDL coding, analog/gate/switch level simulation, mask layout, design rule checking (DRC), layout-versus-schematic (LVS), timing verification and chip testing. Tools Experience with an array of tools from Mentor Graphics, Cadence, Innoveda, Avanti, Tanner Research, Exemplar, Aldec, Mathworks and more. Technology Complementary metal-oxide semiconductor (CMOS) and silicon-on-insulator (SOI) experience with some limited use of bipolars. Designs processed at TSMC, HP, Tower, Intel, AMI, Orbit, Kopin and MIT down to 0.08 µm and including analog processes that include explicit bipolar transistors and capacitors. |
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