Biomorphic VLSI, Inc., Westlake Village, CA (1997-2001).
4Developed several versions of a low-power, low voltage, CMOS 10-bit video rate A/D.
4Assisted in every aspect of 0.5 to 0.25 µm. XVGA to CIF size CMOS imager development including pixel design, correlated double sampling (CDS) readout, programmable gain amplifiers, video-rate analog-to-digital conversion, gamma correction and exposure control using Cadence Composer and Innoveda Viewdraw, Synopsys HSpice and Tanner L-Edit.
4Developed a complete I/O padframe that included complete vendor qualified ESD protection.
4Developed several DRC rule files for a variety of submicron CMOS processes.

MIT Lincoln Laboratory, Lexington, MA (1996-1999, 2002)
4Designed and developed the readout circuitry for a sub-nanosecond imaging IC.
4Researched, designed and fabricated low-power, high-voltage charge-coupled device (CCD) rate-limited clock drivers in a standard CMOS process.
4Evaluated high speed, low-power approaches to low-voltage differential signal I/O.
4Designed an 8 x 8 x 16 bit 0.1 µm. SOI based 5-count multiplier.

Rockwell International Science Center, Thousand Oaks, CA (1995-1997)
4Assisted in the development of smart focal plane CMOS imagers for intelligent vehicle monitoring and control including design entry, circuit simulation and cell layout.