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 Professional ResumePublications 4J.A. Feldman, S.L. Garverick, F.M. Rhodes and J.R. Mann, "A Wafer-Scale Integration Systolic Processor for Connected Word Recognition", IEEE ICASSP, San Diego, CA, Vol. II, pp. 25B.4.1-3, 1984. 4J.Mann, F. M. Rhodes, "A Wafer-Scale DTW Multiprocessor", IEEE ICASSP, Tokyo, Vol. 3, pp.1557-1560, 1986. 4J. Raffel, J. Mann, B. Berger, A. Soares, S. Gilbert, "A Generic Architecture for Wafer-Scale Neuromorphic Computing", IEEE ICNN, 1987 4J. Mann, J. Raffel, R. Lippmann, B. Berger, "A Self-Organizing Neural Net Chip", Neural Networks for Computing, Snowbird, Utah, April 6-9, 1988. |
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